任職資格

•Experience with PLL/CDR design including building blocks (VCO, charge pump, divider, etc.).

•Modeling of CDR and adaptive loops.

•Knowledge of ESD requirements.

•MS with 3+ year experience working on high speed SERDES circuits in advanced CMOS process nodes.

•Architecture experience with transceiver equalizers (TX FIR, RX analog FFE, CTLE, and DFE) – DSP (FFE and DFE)

*請利用下列兩種方式投遞履歷，若您的資格符合職缺所需，我們的獵頭顧問將會盡速與您聯繫 ，謝謝！