職務要求

- RTL/Logic Integration and Verification

- Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top level including SOC.

- Use cdc tool to check RTL/SDC quality

- Hands-on experience on post-silicon debug

任職資格

- Knowledge and design experience of digital flows & FPGA validations

- One of the Key Serdes protocol (PCIe, SATA, USB, VBO, MIPI etc.)

- Knowledge and design experience of PCS

*請利用下列兩種方式投遞履歷，若您的資格符合職缺所需，我們的獵頭顧問將會盡速與您聯繫 ，謝謝！